Digital VLSI Techniques Syllabus — Government College of Engineering…
Full syllabus, topics and curated resources for Digital VLSI Techniques (Government College of Engineering and Technology, Jammu).
MOSFET fundamentals and scaling, static and dynamic CMOS design styles, VLSI physical design, high-performance logic families, MOS memory design, and low-power VLSI design techniques
- Subject code: ECT-1701
- University: Government College of Engineering and Technology, Jammu
- Course: BE (2022 onwards)
- Branch: ECE
- Semester: 7
Digital VLSI Techniques syllabus
Unit 1: MOSFETs
- Enhancement Mode MOSFETs
- Depletion Mode MOSFETs
- Weak and Strong Inversion Conditions
- Threshold Voltage Concept
- Current-Voltage (I-V) Characteristics of MOSFET
- Limitations in I-V Model and MOSFET Parasitics
- Trends and Projections in VLSI Design and Technology
- Flow of VLSI Circuit Design
- Scaling in MOS Devices
Unit 2: VLSI Design Styles
- NMOS and CMOS Process Flow
- Noise Margin
- Inverter Threshold Voltage
- NMOS Inverter Design and Characteristics
- CMOS Inverter Design and Properties
- Delay and Power Dissipation
- Parallel and Series Equivalent Circuits
- Static CMOS Circuit Design
Unit 3: VLSI Physical Design
- Stick Diagrams
- Physical Design Rules
- Layout Designing
- Euler's Rule for Physical Design
- Reliability Issues in CMOS VLSI
- Latching
Unit 4: High Performance Logics
- Precharge-Evaluate Logic
- Dynamic CMOS Logic
- NORA Logic
- Complementary Pass Logic (CPL)
- Transmission Gate Logic
Unit 5: MOS Memory Design
Unit 6: Low Power VLSI Design Techniques
- Need for Low Power VLSI Chips
- Sources of Power Dissipation in Digital ICs
- Physics of Power Dissipation in CMOS Devices
- Dynamic Power Dissipation in CMOS
- Leakage Power Dissipation
- Low Power Figure of Merits
- Impact of Technology Scaling
- Device Innovation and Channel Engineering