Device Innovation and Channel Engineering — Study Resources & PYQs
Device innovation and channel engineering for low power
- Estimated study time: 37 minutes
Study resources
- Low power VLSI design Research Papers index — Academia.edu (leakage/scaling literature review) (Article) — Low power VLSI design Research Papers index — Academia.edu (leakage/scaling literature review) — selected for the syllabus topic Device Innovation and Channel Engineering.
- NPTEL Low Power VLSI Circuits & Systems, IIT Kharagpur (Article) — NPTEL course covering MOS transistors, MOS inverters, static/dynamic CMOS, MOS memories, switching/dynamic/leakage power, voltage scaling and low-power logic.
Taught in these subjects
- Digital VLSI Techniques — ECT-1701 · Government College of Engineering and Technology, Jammu