Transistor Stacking — Study Resources & PYQs
Transistor stacking technique for leakage reduction
- Estimated study time: 50 minutes
Study resources
- Low Power Design Techniques for Reduction of Leakage Power — IJECT (transistor stacking, dual-Vt stacking hybrid) (PDF) — Low Power Design Techniques for Reduction of Leakage Power — IJECT (transistor stacking, dual-Vt stacking hybrid) — selected for the syllabus topic Transistor Stacking.
- NPTEL Low Power VLSI Circuits & Systems, IIT Kharagpur (Article) — NPTEL course covering MOS transistors, MOS inverters, static/dynamic CMOS, MOS memories, switching/dynamic/leakage power, voltage scaling and low-power logic.
Taught in these subjects
- Digital VLSI Techniques — ECT-1701 · Government College of Engineering and Technology, Jammu