NMOS and CMOS Process Flow — Study Resources & PYQs
NMOS and CMOS fabrication process flow
- Estimated study time: 68 minutes
Study resources
- LECTURE NOTES ON Basic VLSI Design — VEMU Institute (NMOS/CMOS process, depletion mode load section) (PDF) — LECTURE NOTES ON Basic VLSI Design — VEMU Institute (NMOS/CMOS process, depletion mode load section) — selected for the syllabus topic NMOS and CMOS Process Flow.
- NPTEL Low Power VLSI Circuits & Systems, IIT Kharagpur (Article) — NPTEL course covering MOS transistors, MOS inverters, static/dynamic CMOS, MOS memories, switching/dynamic/leakage power, voltage scaling and low-power logic.
NMOS and CMOS Process Flow previous year questions
- What do you mean by n-MOS fabrication and discuss in detail the CMOS fabrication using n-well process.
- Draw and explain the CMOS logic circuit of the following: a. RS Latch using NOR gates. b. Clocked RS FLIP FLOP
- Draw and explain the CMOS logic circuit of the following: a. 2 x 1 multiplexer b. Full adder
- Give the CMOS designs of XOR and XNOR gates and explain their working.
- Show the complete fabrication steps including flow chart of CMOS using p-well process.
Taught in these subjects
- Digital VLSI Techniques — ECT-1701 · Government College of Engineering and Technology, Jammu