Scaling in MOS Devices — Study Resources & PYQs
Scaling in MOS devices
- Estimated study time: 40 minutes
Study resources
- UNIT-3 VLSI CIRCUIT DESIGN PROCESS — SlideShare (VLSI design flow, MOS layers, scaling of MOS) (PDF) — UNIT-3 VLSI CIRCUIT DESIGN PROCESS — SlideShare (VLSI design flow, MOS layers, scaling of MOS) — selected for the syllabus topic Scaling in MOS Devices.
- NPTEL Low Power VLSI Circuits & Systems, IIT Kharagpur (Article) — NPTEL course covering MOS transistors, MOS inverters, static/dynamic CMOS, MOS memories, switching/dynamic/leakage power, voltage scaling and low-power logic.
Scaling in MOS Devices previous year questions
Taught in these subjects
- Digital VLSI Techniques — ECT-1701 · Government College of Engineering and Technology, Jammu