Circuit Techniques for Leakage Power Reduction — Study Resources & PY…
Circuit techniques for leakage power reduction
- Estimated study time: 50 minutes
Study resources
- Low Power Design Techniques for Reduction of Leakage Power — IJECT (transistor stacking, dual-Vt stacking hybrid) (PDF) — Low Power Design Techniques for Reduction of Leakage Power — IJECT (transistor stacking, dual-Vt stacking hybrid) — selected for the syllabus topic Circuit Techniques for Leakage Power Reduction.
- LEAKAGE POWER REDUCTION AND ANALYSIS OF... — International Journal of VLSI Design & Communication Systems (PDF) — LEAKAGE POWER REDUCTION AND ANALYSIS OF... — International Journal of VLSI Design & Communication Systems — selected for the syllabus topic Circuit Techniques for Leakage Power Reduction.
Taught in these subjects
- Digital VLSI Techniques — ECT-1701 · Government College of Engineering and Technology, Jammu