Latching — Study Resources & PYQs
Latch-up and latching issues in CMOS VLSI
- Estimated study time: 50 minutes
Study resources
- ROHINI COLLEGE OF ENGINEERING — EC 8095 VLSI Design notes (dynamic circuit charge leakage, latch-up context) (PDF) — ROHINI COLLEGE OF ENGINEERING — EC 8095 VLSI Design notes (dynamic circuit charge leakage, latch-up context) — selected for the syllabus topic Latching.
- NPTEL Low Power VLSI Circuits & Systems, IIT Kharagpur (Article) — NPTEL course covering MOS transistors, MOS inverters, static/dynamic CMOS, MOS memories, switching/dynamic/leakage power, voltage scaling and low-power logic.
Taught in these subjects
- Digital VLSI Techniques — ECT-1701 · Government College of Engineering and Technology, Jammu