Flip-Flops and Latches Design — Study Resources & PYQs
Low power flip-flop and latch design
- Estimated study time: 50 minutes
Study resources
- A new leakage reduction method for ultra low power VLSI design for portable devices — ResearchGate (MTCMOS flip-flop implementations) (Article) — A new leakage reduction method for ultra low power VLSI design for portable devices — ResearchGate (MTCMOS flip-flop implementations) — selected for the syllabus topic Flip-Flops and Latches Design.
- NPTEL Low Power VLSI Circuits & Systems, IIT Kharagpur (Article) — NPTEL course covering MOS transistors, MOS inverters, static/dynamic CMOS, MOS memories, switching/dynamic/leakage power, voltage scaling and low-power logic.
Flip-Flops and Latches Design previous year questions
Taught in these subjects
- Digital VLSI Techniques — ECT-1701 · Government College of Engineering and Technology, Jammu