Digital VLSI Techniques 2018 Question Paper — Government College of E…
The 2018 Digital VLSI Techniques previous year question paper (Government College of Engineering and Technology, Jammu), with every question and its marks.
- University: Government College of Engineering and Technology, Jammu
- Subject: Digital VLSI Techniques
- Course: VLSI DESIGN AND TECHNOLOGY
- Branch: E & C Engg.
- Year: 2018
- Paper: end-term
- Duration: 180 minutes
- Total marks: 100
Instructions
- Attempt any five questions, selecting at least two questions from each section.
- All questions carry equal marks.
- Assume any necessary data.
- Use of calculator is allowed.
Questions
Section A
- Q1. (a) What is ion implantation ? What are the advantages and disadvantages of this process over diffusion process ? (b) Explain briefly the Twin Tub Process. [20 marks]
- Q2. Explain any five non-ideal effects of MOSFET. [20 marks]
- Q3. Show the complete fabrication steps including flow chart of CMOS using p-well process. [20 marks]
- Q4. Explain the following : (a) VLSI design flow. (b) CMOS inverter layout design. [20 marks]
Section B
- Q5. (a) Discuss in detail the operation of a CMOS inverter. (b) Differentiate between Enhancement and Depletion Pull ups. [20 marks]
- Q6. Discuss the following : (a) Power dissipation of CMOS inverter. (b) Delay of CMOS inverter. (c) Noise Margin of CMOS inverter. [20 marks]
- Q7. Draw and explain the following using CMOS logic circuit : (a) NAND gate. (b) OR gate. (c) 2 to 1 Multiplexer. [20 marks]
- Q8. Draw and explain the following using CMOS logic circuit : (a) Clocked JK Flip Flop. (b) Clocked D Flip Flop. [20 marks]
Related pages
Other years
- Digital VLSI Techniques 2018 question paper — end-term
- Digital VLSI Techniques 2018 question paper — end-term