Digital VLSI Techniques 2018 Question Paper — Government College of E…
The 2018 Digital VLSI Techniques previous year question paper (Government College of Engineering and Technology, Jammu), with every question and its marks.
- University: Government College of Engineering and Technology, Jammu
- Subject: Digital VLSI Techniques
- Course: VLSI
- Branch: Electronics & Communication Engineering
- Year: 2018
- Paper: end-term
- Duration: 180 minutes
- Total marks: 100
Instructions
- Attempt five questions in all selecting at least two questions from each Section.
- Use of Calculator is allowed.
- Assume appropriate data if not given.
- Each question carries 20 marks.
Questions
Section – A
- Q1. What do you mean by n-MOS fabrication and discuss in detail the CMOS fabrication using n-well process. [20 marks]
- Q2. Write the VHDL and verilog code of the following: a. 2-bit comparator b. 2 to 4 line decoder [20 marks]
- Q3. a. Draw the drain and transfer characteristics of n-MOSFET of enhancement type. b. Show the comparison of constant field scaling and constant voltage scaling. [20 marks]
- Q4. Write short note on the following: a. Layout design rules. b. VLSI design flow [20 marks]
Section – B
- Q5. Draw and explain the CMOS logic circuit of the following: a. RS Latch using NOR gates. b. Clocked RS FLIP FLOP [20 marks]
- Q6. Draw and explain the CMOS logic circuit of the following: a. 2 x 1 multiplexer b. Full adder [20 marks]
- Q7. Discuss the voltage transfer characteristics of CMOS inverter and also discuss the switching power dissipation of CMOS invereter. [20 marks]
- Q8. Write short note on the following: a. Power delay product b. Calculation of delay times [20 marks]
Related pages
Other years
- Digital VLSI Techniques 2018 question paper — end-term
- Digital VLSI Techniques 2018 question paper — end-term