Digital VLSI Techniques 2018 Question Paper — Government College of E…
The 2018 Digital VLSI Techniques previous year question paper (Government College of Engineering and Technology, Jammu), with every question and its marks.
- University: Government College of Engineering and Technology, Jammu
- Subject: Digital VLSI Techniques
- Course: VLSI Design & Technology
- Branch: E & C ENGINEERING
- Year: 2018
- Paper: end-term
- Duration: 180 minutes
- Total marks: 100
Instructions
- Attempt five questions in all selecting at least two questions from each Section.
- Assume any necessary data.
- Each question carries 20 marks.
Questions
Section - A
- Q1. With net flow chart, explain Twin-Tub fabrication processes. What are its advantages over N-well and P-well fabrication processes? [20 marks]
- Q2. Explain the steps of oxidation and metallization of MOS fabrication process. [20 marks]
- Q3. (a) Explain the operation of comparator. What are its applications? (b) Using data flow modeling, write the VHDL program for 2-bit comparator. [20 marks]
Section - B
- Q4. What is MOSFET scaling? Explain four short channel effects, which take place in MOSFET due to the downscaling. [20 marks]
- Q5. (a) Explain the switching characteristic of CMOS inverter. (b) Explain Fan-In and Fan-out of digital circuits. [20 marks]
- Q6. Give the CMOS designs of XOR and XNOR gates and explain their working. [20 marks]
- Q7. Give the simple static CMOS logic circuit for the function F, where $F = \overline{ABCD} + (\overline{ACD} + \overline{ABC}) + \overline{BCD}$. Hence find the number of transistors used. [20 marks]
- Q8. Give the static CMOS design of positive and negative Latches. [20 marks]
Related pages
Other years
- Digital VLSI Techniques 2018 question paper — end-term
- Digital VLSI Techniques 2018 question paper — end-term