Memory Interfacing and Hierarchy (GATE CS) — GATE Computer Science an…
Instruction set and addressing modes. Design of arithmetic and logic unit (ALU). Design of control unit - hardwired and microprogrammed. Memory interfacing and hierarchy: performance, cache memory mapping. I/O interface (interrupt and DMA). Instruction pipelining, pipeline hazards.
- Exam: GATE Computer Science and Information Technology (CS)
- Section: Computer Organization and Architecture